ATmega88 datasheet писал(а):6.The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7.The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega48/88/168 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega48/88/168 devices, as well as any other device with a proper tLOW acceptance margin.
AVRfreaks писал(а):Any AVR with a TWI module:
TWI formula error: This (1/Fscl-2/Fck) formula appears in many data sheets Electrical Characteristics section, Two-wire Serial Interface Characteristics in notes 6 and 7. The formula is supposed to be (1/2*Fscl-2/Fck). The Tlow time period calculations work correctly with the new formula.
For note 6:
ATMEL support wrote:
Fck=6 MHz gives 4.67uS
Fck=7 MHz gives 4.71uS
So the idea was that Fck needed to be higher than 6MHz (or close to 7MHz) to meet these requirements.
BTW, newer versions of some of the above data sheets have already been released and the above errors have still not been fixed. The errors were reported to ATMEL and acknowledged as data sheet errors, but have never been dealt with. I fully intend to remove the above data sheet error information when (if) the data sheets actually get fixed. The initial JTD program example error was first acknowledged by ATMEL on March 10, 2005, has been re-reported and is now over 3 years old and counting Shocked. Now brand new data sheets have copied this same bug again Confused. However, three problems reported in the Attiny24/44/84 data sheet were fixed in less than two weeks. I do not understand what is going wrong at ATMEL, but something very important is badly broken.
И не всегда понятно, в каких режимах какие тайминги применимы...
Кроме того есть разные странные упоминания в разных даташитах, которые _могут_ зависеть от чипа и ревизии:
Например отчет об исправлениях в ATmega32:
TWCR Write Operation Ignored when Immediately Repeated
In ATmega32 consecutive write operations to the TWCR Register work as expected, and there is no need to insert a NOP in between
TWI is Speed Limited in Slave Mode
The speed limit in Slave mode does not apply to ATmega32. In ATmega32, the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency, as described in the datasheet.
То есть видно, что какие-то проблемы были, раз их пришлось исправлять. В каких кристаллах и каких ревизиях
торчат уши, можно только гадать...
Можно еще почитать AVR316: SMbus Slave Using the TWI Module - там немножко "в сторону", но по сути то же самое.
Вообще, имхо, как реализован I2C в АВР-ках можно описать несколькими словами... и все непечатные.