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PROSPICE Release 6.9 SP5 (C) Labcenter Electronics 1993-2006.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
Reading netlist...
Reading SPICE models...
Building circuit...
Instantiating SPICE models...
[U1] PIC18 model release 6.9 SP5 simulating 'PIC18F452' device.
[U1] Loaded 256 bytes of persistent EEPROM data.
[U1] Loading PIC18 COFF file 'USART.COF'.
Warning: [U1] Could not load source file 'C:\MCC18\src\traditional\startup\c018i.c'.
[U1] Loaded 420 program bytes and 0 data bytes.
[U1] Execution (instruction) clock frequency is 40.0MHz
Warning: [U1] at 100.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 200.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 300.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 400.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 500.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 600.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 700.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 800.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 900.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
PROSPICE Release 6.9 SP5 (C) Labcenter Electronics 1993-2006.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
Reading netlist...
Reading SPICE models...
Building circuit...
Instantiating SPICE models...
[U1] PIC18 model release 6.9 SP5 simulating 'PIC18F452' device.
[U1] Loaded 256 bytes of persistent EEPROM data.
[U1] Loading PIC18 COFF file 'USART.COF'.
Warning: [U1] Could not load source file 'C:\MCC18\src\traditional\startup\c018i.c'.
[U1] Loaded 420 program bytes and 0 data bytes.
[U1] Execution (instruction) clock frequency is 40.0MHz
[U1]
[U1] Device Information:
[U1] Model File.................................................: C:\Program Files\MICRO\PROT\Models\PIC18.DLL
[U1] Model Version..............................................: 6.9 SP5
[U1] Model Build Date/Time......................................: Aug 10 2006 15:55:21
[U1] PIC Device.................................................: PIC18F452
[U1] Code memory (bytes)........................................: 32768
[U1] Data memory (bytes)........................................: 1536
[U1] EEPROM memory (bytes)......................................: 256
[U1] Code memory is writable (Flash)............................: Yes
[U1] Width of code memory erased per operation (bytes)..........: 64
[U1] Width of code memory written per operation (bytes).........: 8
[U1] Number of bytes of bank 0 GPR in access bank...............: 128
[U1] Number of external interrupts (INT0, INT1, etc.)...........: 3
[U1] Physically present PORTA pins..............................: RA0-RA6
[U1] Physically present PORTB pins..............................: RB0-RB7
[U1] Physically present PORTC pins..............................: RC0-RC7
[U1] Physically present PORTD pins..............................: RD0-RD7
[U1] Physically present PORTE pins..............................: RE0-RE2
[U1] Physically present PORTF pins..............................: None
[U1] Physically present PORTG pins..............................: None
[U1] Physically present PORTH pins..............................: None
[U1] Physically present PORTJ pins..............................: None
[U1] ADC channels available.....................................: CH0-CH7
[U1] ADC Channel Resolution.....................................: 10-bit
[U1] Has watchdog timer.........................................: Yes
[U1] Has timers 0/1/2/3/4/5.....................................: Yes, Yes, Yes, Yes, No, No
[U1] Has (E)CCP module 1........................................: Standard
[U1] Has (E)CCP module 2........................................: Standard
[U1] Has (E)CCP module 3........................................: No
[U1] Has (E)CCP module 4........................................: No
[U1] Has (E)CCP module 5........................................: No
[U1] Has Parallel Slave Port (PSP)..............................: Yes
[U1] Has Master Sync. Serial Port (MSSP)........................: Yes
[U1] Has (E)USART module 1......................................: Standard
[U1] Has (E)USART module 2......................................: No
[U1] Device ID is...............................................: 0b00000100 0b00100011
[U1]
[U1] Device Configuration From Component Properties:
[U1] Q-clock period.............................................: 25ns (40MHz)
[U1] Instruction clock period...................................: 100ns (10MHz)
[U1] Watchdog Timer Period......................................: 18ms
[U1] Minimum ADC acquisition time...............................: 20us
[U1] Internal ADC RC-clock period ..............................: 4us
[U1] ADC sample delay...........................................: 100ns
[U1] Data EEPROM write delay....................................: 10ms
[U1] Code EEPROM write delay....................................: 2ms
[U1] Code EEPROM erase delay....................................: 2ms
[U1] MCLR pin poll delay........................................: 100ms
[U1] Treat warnings as errors and abort simulation..............: No
[U1] Disable WDT regardless of actual device configuration......: Yes
[U1] Force simulation breakpoint at ADC sample time.............: No
[U1] Simulate start-up delays (on reset)........................: No
[U1] Simulate wake-up delays (on coming out of sleep)...........: No
[U1] Generate clock on CLKO pin.................................: No
[U1] Warn about MOVFF with PC/TOSx and interrupts...............: No
[U1] Warn about illegal memory accesses.........................: Yes
[U1] Warn about illegal opcode execution........................: Yes
[U1] Warn about ADC timing and channel selection errors.........: No
[U1] Dump register information on reset.........................: No
[U1]
[U1] Device Configuration From CONFIG Registers:
[U1] Dump of PIC18F452 configuration bytes:
[U1] Oscillator type..............................(FOSCx).......: HSPLL
[U1] Oscillator system clock switch enabled.......(OSCSEN)......: No
[U1] Stack under/overflow causes reset............(STVREN)......: Yes
[U1] Power-up timer enabled.......................(PWRTEN)......: No
[U1] PORTA availability mask......................(PORTA<7:0>)..: 00111111
[U1] CCP2 pin is multiplexed with.................(CCP2MX)......: PORTC<1>
[U1] Watchdog timer enabled.......................(WDTEN).......: Yes
[U1] Watchdog timer prescaler.....................(WDTPSx)......: 128:1
[U1] EPROM data is write-protected................(WRTD)........: No
[U1] Configuration Registers Are Write-protected..(WRTC)........: No
[U1] Code 0x000000-0001FF is write-protected......(WRTB)........: No
[U1] Code 0x000200-001FFF is write-protected......(WRT0)........: No
[U1] Code 0x002000-003FFF is write-protected......(WRT1)........: No
[U1] Code 0x004000-005FFF is write-protected......(WRT2)........: No
[U1] Code 0x006000-007FFF is write-protected......(WRT3)........: No
Warning: [U1] at 100.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 200.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
Warning: [U1] at 300.000m (PC=0x0000): $MCLR$ is low. Processor is in reset.
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