Ну я вот посниффал их обмен чуток, там пипец. Старенький я уже для этого...
Добавлено спустя 1 час 19 минут 56 секунд:Если я правильно разобрал конфигурацию, то они на 909МГц работают
Код:
[0x34(0xFF)]
[0x03(0xFF)]
[0x50(0xFF)0x00(0x00)0x00(0x00)]
[0x00(0x00)0x00(0x00)]
[0x34(0x00)]
[0x08(0x00)]
[0x34(0xFF)0x03(0xFF)]
/* set XTAL freq: 30,000,000 */
[0x02(0xFF)0x01(0xFF)0x00(0xFF)0x01(0xFF)0xC9(0xFF)]
[0xC3(0xFF)]
[0x80(0xFF)]
/* set property
group = 0
num_props = 0x08
start_prop = 0x00
[0x11(0xFF)0x00(0xFF)0x08(0xFF)0x00(0xFF)
0x40(0xFF) //Configure the internal capacitor frequency tuning bank for the crystal oscillator.
0x71(0xFF) // Divided system clock output is enabled., Clock output is system clock divided by 30., 32 kHz clock is driven by internal RC oscillator.
0x0A(0xFF) //GLOBAL_LOW_BATT_THRESH
0x61(0xFF)] //TX and RX FIFO are independent, 64-byte size for each other., Packet format is generic, no dynamic reprogramming of packet handler properties. Low power mode for RX and TX.
[0x06(0xFF)] //GLOBAL_WUT_CONFIG
[0x08(0xFF)] //GLOBAL_WUT_M
[0x00(0xFF)] //GLOBAL_WUT_R
[0x62(0xFF) //GLOBAL_WUT_LDC
0x11(0xFF)0x20(0xFF)0x02(0xFF)0x00(0xFF)]
[0x03(0xFF)] // MODEM TYPE: 2GFSK
[0x80(0xFF)] // Adjust Sync Word timeout for Manchester coding.
[0x11(0xFF)0x20(0xFF)0x01(0xFF)][0x19(0xFF)]
[0x80(0xFF)] // MODEM_MDM_CTRL: Input from detector's output.
[0x11(0xFF)0x20(0xFF)0x01(0xFF)][0x4C(0xFF)]
[0x12(0xFF)] // MODEM_RSSI_CONTROL: The RSSI value is updated at 1*Tb bit period intervals but always reflects the average value over the previous 2*Tb bit periods.
// Latches RSSI at Sync Word detect.
[0x11(0xFF)0x40(0xFF)0x06(0xFF)0x00(0xFF)
0x3B(0xFF) // Frac-N PLL Synthesizer integer divide number. : 59
0x0C(0xFF) // Frequency control fractional part
0xE8(0xFF)] // Frequency control fractional part
[0x1B(0xFF)] // Frequency control fractional part : 845851
[0x0D(0xFF)] // FREQ_CONTROL_CHANNEL_STEP_SIZE
[0xA7(0xFF)] // FREQ_CONTROL_CHANNEL_STEP_SIZE : 3495
NPRESC MODEM_CLKGEN_BAND: High Performance mode (fixed prescaler = Div-by-2). (DEFAULT)
OUTDIV Output is FVCO/4. (DEFAULT) 900 MHz band.
RFch = (59 + 1.613332748) * (2 * 30MHz/4) = 909.19999122 MHz
[0x11(0xFF)0x10(0xFF)0x08(0xFF)0x01(0xFF)
0x10(0xFF)
0x00(0xFF)
0x0F(0xFF)
0x3E(0xFF)]
[0x00(0xFF)]
[0x00(0xFF)]
[0x00(0xFF)]
[0x00(0xFF)
0x11(0xFF)0x11(0xFF)0x03(0xFF)0x00(0xFF)
0x01(0xFF)]
[0x4B(0xFF)]
[0xD4(0xFF)]
[0x11(0xFF)0x12(0xFF)0x01(0xFF)][0x00(0xFF)]
[0x85(0xFF)]
[0x11(0xFF)0x12(0xFF)0x01(0xFF)][0x06(0xFF)]
[0x0A(0xFF)]
[0x11(0xFF)0x12(0xFF)0x03(0xFF)0x08(0xFF)]
[0x0A(0xFF)]
[0x01(0xFF)]
[0x00(0xFF)]
[0x11(0xFF)0x12(0xFF)0x08(0xFF)0x0D(0xFF)
0x00(0xFF)
0x01(0xFF)
0x01(0xFF)]
[0x82(0xFF)]
[0x00(0xFF)]
[0x3F(0xFF)]
[0x01(0xFF)
0x0A(0xFF)
/* GPIO Pin Cfg */
0x13(0xFF)
0x07(0xFF) // GPIO0 no pullup, Divided MCU clock.
0x00(0xFF)] // GPIO1 no pullup, Do not modify the behavior of this pin.
[0x1A(0xFF)] // GPIO1 no pullup, 26 = High when a sync word is detected. TODO: What clears this
[0x18(0xFF)] // GPIO2 no pullup, 24 = High when a valid preamble is detected. Cleared when sync is received.
[0x11(0xFF) // GPIO3 no pullup, 17 = RX data CLK output to be used in conjuction with RX Data pin.
0x02(0xFF) // NIRQ: 2 = CMOS output driven low.
0x04(0xFF) // SDO_PULL: 4 = CMOS input.
0x00(0xFF) // Gen_CFG: 0 = GPIOs configured as outputs will have highest drive strength.
0x03(0xFF)]
[0x0A(0xFF)]
[0x09(0xFF)]
[0x07(0xFF)0x11(0xFF)0x01(0xFF)0x02(0xFF)]
[0x00(0xFF)]
[0x01(0xFF)]
[0x18(0xFF)]
[0x11(0xFF)0x20(0xFF)0x07(0xFF)0x2C(0xFF)
0x04(0xFF) //MODEM_AFC_GEAR
0x47(0xFF)] //MODEM_AFC_WAIT
[0x82(0xFF)] //MODEM_AFC_GAIN
[0x5D(0xFF)] //MODEM_AFC_LIMITER
[0x03(0xFF)] //MODEM_AFC_MISC
[0xC7(0xFF) //MODEM_AFC_ZIFOFF
0xC0(0xFF) //MODEM_ADC_CTRL
0x11(0xFF)0x20(0xFF)0x01(0xFF)0x35(0xFF)]
[0xE2(0xFF)] //MODEM_AGC_CONTROL
[0x11(0xFF)0x20(0xFF)0x03(0xFF)0x38(0xFF) //Auto Gain Ctrl
0x21(0xFF)] //MODEM_AGC_WINDOW_SIZE
[0x15(0xFF)] //MODEM_AGC_RFPD_DECAY
[0x15(0xFF)] //MODEM_AGC_IFPD_DECAY
[0x11(0xFF)0x20(0xFF)0x08(0xFF)0x22(0xFF) //Bit Clock Recovery
0x00(0xFF) //MODEM_BCR_OSR
0x90(0xFF)
0x03(0xFF)
0x12(0xFF)
0x6F(0xFF)]
[0x01(0xFF)]
[0xC7(0xFF)]
[0x02(0xFF)
0x11(0xFF) 0x20(0xFF)0x02(0xFF)0x2A(0xFF)]
[0xC2(0xFF)]
[0x00(0xFF)]
[0x11(0xFF)0x20(0xFF)0x02(0xFF)0x1E(0xFF)] //MODEM_DECIMATION_CFG1 Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
[0x00(0xFF)]
[0x30(0xFF)]
[0x11(0xFF)0x20(0xFF)0x08(0xFF)0x40(0xFF) //Configures the attack and decay times of the OOK Peak Detector.
0x29(0xFF)
0x0C(0xFF)
0xA4(0xFF)]
[0x02(0xFF)]
[0xD6(0xFF)]
[0x83(0xFF)]
[0x01(0xFF)0x8E(0xFF)
0x11(0xFF)0x23(0xFF)0x08(0xFF)0x00(0xFF) // filters, charge pump
0x39(0xFF)
0x04(0xFF)
0x0B(0xFF)]
[0x05(0xFF)]
[0x04(0xFF)]
[0x01(0xFF)]
[0x03(0xFF)
0x05(0xFF)
0x11(0xFF)0x20(0xFF)0x01(0xFF)0x4E(0xFF)] //RSSI compensation value.
[0x21(0xFF)]
/* Calibrate receiver image rejection for Si4463 and Si4464. */
[0x17(0xFF)
0x56(0xFF)
0x10(0xFF)
0xFA(0xFF)]
[0xF0(0xFF)]
/* Calibrate receiver image rejection for Si4463 and Si4464. */
[0x17(0xFF)
0x13(0xFF)
0x10(0xFF)
0xFA(0xFF)]
[0xF0(0xFF)]
[0x50(0xFF)0x00(0x02)0x00(0x00)]
[0x00(0x03)0x00(0x14)]
/* Provides access to transmit and receive fifo counts and reset. */
[0x15(0x00)] // CMD
[0x03(0x00)] // FIFO - both Rx and Tx
/* Switches to RX state. Command arguments are retained though sleep state, so these only need to
be written when they change. */
[0x32(0xFF)
0x00(0xFF) // channel = 0
0x00(0xFF) // start immediately
0x00(0xFF)0x00(0xFF)] // RX LEN = 0
[0x00(0xFF)] // NEXT STATE: NO CHANGE
[0x00(0xFF)] // NEXT STATE: NO CHANGE
[0x00(0xFF)] // NEXT STATE: NO CHANGE
[0x50(0xFF)0x00(0x02)]
[0x00(0x00)]
[0x00(0x08)]
[0x00(0x14)]
[0x50(0xFF)0x00(0x02)]
[0x00(0x00)]
[0x00(0x08)]
[0x00(0x14)]
Добавлено спустя 13 минут 13 секунд:Короче можно помаятся - перепрошить мегу, перенастроить частоту на 433 или 315 МГц и посмотреть, что там прилетает с брелков...
Думаю дуиновский бутлоадер туда что ли зашить как-нить?
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