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PROSPICE Release 6.9 SP5 (C) Labcenter Electronics 1993-2006.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
Reading netlist...
Reading SPICE models...
Building circuit...
Instantiating SPICE models...
[U1] PIC18 model release 6.9 SP5 simulating 'PIC18F452' device.
[U1] Loaded 256 bytes of persistent EEPROM data.
[U1] Loading PIC18 COFF file 'USART.COF'.
Warning: [U1] Could not load source file 'C:\MCC18\src\traditional\startup\c018i.c'.
[U1] Loaded 420 program bytes and 0 data bytes.
[U1] Execution (instruction) clock frequency is 40.0MHz
DSIM WARNING: Contention on net [#00002] at time 0.0001067. State=2E
DSIM WARNING: Contention on net [#00002] at time 0.0004139. State=2E
DSIM WARNING: Contention on net [#00002] at time 0.0006187. State=2E
DSIM WARNING: Contention on net [#00002] at time 0.0008235. State=2E
[U1] Processor has been reset by watchdog timer expiring at time 2.304000.
DSIM WARNING: Contention on net [#00002] at time 2.30411. State=2E
DSIM WARNING: Contention on net [#00002] at time 2.30441. State=2E
DSIM WARNING: Contention on net [#00002] at time 2.30462. State=2E
DSIM WARNING: Contention on net [#00002] at time 2.30482. State=2E
[U1] Processor has been reset by watchdog timer expiring at time 4.608000.
DSIM WARNING: Contention on net [#00002] at time 4.60811. State=2E
DSIM WARNING: Contention on net [#00002] at time 4.60841. State=2E
DSIM WARNING: Contention on net [#00002] at time 4.60862. State=2E
DSIM WARNING: Contention on net [#00002] at time 4.60882. State=2E

PROSPICE Release 6.9 SP5 (C) Labcenter Electronics 1993-2006.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
Reading netlist...
Reading SPICE models...
Building circuit...
Instantiating SPICE models...
[U1] PIC18 model release 6.9 SP5 simulating 'PIC18F452' device.
[U1] Loaded 256 bytes of persistent EEPROM data.
[U1] Loading PIC18 COFF file 'USART.COF'.
Warning: [U1] Could not load source file 'C:\MCC18\src\traditional\startup\c018i.c'.
[U1] Loaded 420 program bytes and 0 data bytes.
[U1] Execution (instruction) clock frequency is 40.0MHz
[U1] Processor has been reset by watchdog timer expiring at time 2.304000.
[U1] Processor has been reset by watchdog timer expiring at time 4.608000.

#include <18F452.h>
#fuses HS,NOWDT,PUT,BROWNOUT,NOLVP, NOPROTECT, CPB
#use delay(clock=10000000)
#use rs232(baud=9600, xmit=PIN_C6, rcv=PIN_C7, ERRORS)

#define ROM_ADDR  0x4000

//====================================
void main(void)
{
int8 i;
int8 write_data[8] = {1,2,3,4,5,6,7,8};
int8 read_data[8]  = {0,0,0,0,0,0,0,0};

printf("Flash write size = %u\n\r", getenv("FLASH_WRITE_SIZE"));
printf("\n\r");

// Erase flash memory.
erase_program_eeprom(ROM_ADDR);

// Read flash memory.
read_program_memory(ROM_ADDR, read_data, sizeof(read_data));

// Display it, to show it's erased.
printf("Flash memory after being erased: ");
for(i = 0; i < sizeof(read_data); i++)
   printf("%X ", read_data[i]);
printf("\n\r");
printf("\n\r");

// Now write 8 bytes.
write_program_memory(ROM_ADDR, write_data, sizeof(write_data));

// Read them back.
read_program_memory(ROM_ADDR, read_data, sizeof(read_data));

// Display data read from Flash memory.
printf("Flash memory after being written: ");
for(i = 0; i < sizeof(read_data); i++)
   printf("%X ", read_data[i]);
printf("\n\r");
printf("\n\r");

while(1);
}