#ifndef ADXL345_H
#define ADXL345_H

#include "stm32f10x_usart.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_i2c.h"
#include "stm32f10x.h"


uint8_t ADXL345_ReadDevID(uint8_t Device7BitAddress);
uint8_t ADXL345_ReadRegister(uint8_t Device7BitAddress, uint8_t RegisterToRead);
void ADXL345_WriteRegister(uint8_t dev_addr, uint8_t reg, uint8_t value);
void ADXL345_GetMeasurements(uint8_t dev_addr, float *values);



/*Interrupts may be bound to either INt1 or INT2*/
#define ADXL345_IntMap_DT_RDY		((uint8_t)0x80)
#define ADXL345_IntMap_SNGL_TAP		((uint8_t)0x40)
#define ADXL345_IntMap_DBL_TAP		((uint8_t)0x20)
#define ADXL345_IntMap_Activity		((uint8_t)0x10)
#define ADXL345_IntMap_Inactivity	((uint8_t)0x08)
#define ADXL345_IntMap_FreeFall		((uint8_t)0x04)
#define ADXL345_IntMap_Watermark	((uint8_t)0x02)
#define ADXL345_IntMap_Overrun		((uint8_t)0x01)

typedef enum {
	ADXL345_FIFOMode_Bypass = 0b00, /*FIFO is bypassed.*/
	ADXL345_FIFOMode_FIFO = 0b01, /*FIFO collects up to 32 values and then stops
									collecting data, collecting new data only when
									FIFO is not full.*/
	ADXL345_FIFOMode_Stream = 0b10, /*FIFO holds the last 32 data values. When FIFO
									*is full, the oldest data is overwritten with
									newer data.*/
	ADXL345_FIFOMode_Trigger = 0b11 /*When triggered by the trigger bit, FIFO holds
									the last data samples before the trigger event
									and then continues to collect data until full.
									New data is collected only when FIFO is not full.*/
} ADXL345_FIFOMode_TypeDef;

typedef struct {
	uint8_t ADXL345_TapThreshold;	/*!<Register 0x1D—THRESH_TAP (Read/Write)
									The THRESH_TAP register is eight bits and holds
									the threshold value for tap interrupts. The data
									format is unsigned, therefore, the magnitude of
									the tap event is compared with the value in
									THRESH_TAP for normal tap detection. The scale
									factor is 62.5 mg/LSB (that is, 0xFF = 16 g).
									A value of 0 may result in undesirable behavior
									if single tap/double tap interrupts are enabled.*/

	uint8_t ADXL345_OFSX_UserOffsetAdjustement; /*!<Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write)
											The OFSX, OFSY, and OFSZ registers are each
											eight bits and offer user-set offset adjustments
											in twos complement format with a scale factor
											of 15.6 mg/LSB (that is, 0x7F = 2 g). The
											value stored in the offset registers is
											automatically added to the acceleration data,
											and the resulting value is stored in the
											output data registers. For additional information
											regarding offset calibration and the use of
											the offset registers, refer to the Offset Calibration
											section of the datasheet.*/

	uint8_t ADXL345_OFSY_UserOffsetAdjustement; /*!<Same as ADXL345_OFSX_UserOffsetAdjustement;*/

	uint8_t ADXL345_OFSZ_UserOffsetAdjustement; /*!<Same as ADXL345_OFSX_UserOffsetAdjustement;*/

	uint8_t ADXL345_EventMaximumDuration;	/*!<Register 0x21—DUR (Read/Write)
											The DUR register is eight bits and contains
											an unsigned time value representing the
											maximum time that an event must be above the
											THRESH_TAP threshold to qualify as a tap
											event. The scale factor is 625 us/LSB. A
											value of 0 disables the single tap/ double
											tap functions.*/

	uint8_t ADXL345_DoubleTapLatency;	/*!<Register 0x22—Latent (Read/Write)
										The latent register is eight bits and contains an
										unsigned time value representing the wait time
										from the detection of a tap event to the start of
										the time window (defined by the window register)
										during which a possible second tap event can be
										detected. The scale factor is 1.25 ms/LSB.
										A value of 0 disables the double tap function.*/

	uint8_t ADXL345_DoubleTapWindow;	/*!<Register 0x23—Window (Read/Write)
										The window register is eight bits and contains an
										unsigned time value representing the amount of
										time after the expiration of the latency time
										(determined by the latent register) during which
										a second valid tap can begin. The scale factor
										is 1.25 ms/LSB. A value of 0 disables the double
										tap function.*/

	uint8_t ADXL345_ActivityDetectThreshold; /*!<Register 0x24—THRESH_ACT (Read/Write)
										The THRESH_ACT register is eight bits and holds
										the threshold value for detecting activity. The
										data format is unsigned, so the magnitude of the
										activity event is compared with the value in the
										THRESH_ACT register. The scale factor is 62.5
										mg/LSB. A value of 0 may result in undesirable
										behavior if the activity interrupt is enabled.*/

	uint8_t ADXL345_InactivityDetectThreshold; /*!<Register 0x25—THRESH_INACT (Read/Write)
										The THRESH_INACT register is eight bits and holds
										the threshold value for detecting inactivity. The
										data format is unsigned, so the magnitude of the
										inactivity event is compared with the value in the
										THRESH_INACT register. The scale factor is 62.5 mg/LSB.
										A value of 0 may result in undesirable behavior if the
										inactivity interrupt is enabled.*/

	uint8_t ADXL345_InactivityDetectMinTime; /*!<Register 0x26—TIME_INACT (Read/Write)
										The TIME_INACT register is eight bits and contains
										an unsigned time value representing the amount of
										time that acceleration must be less than the
										value in the THRESH_INACT register for inactivity
										to be declared. The scale factor is 1 sec/LSB.
										Unlike the other interrupt functions, which use
										unfiltered data (see the Threshold section), the
										inactivity function uses filtered output data.
										At least one output sample must be generated for
										the inactivity interrupt to be triggered. This
										results in the function appearing unresponsive
										if the TIME_INACT register is set to a value less
										than the time constant of the output data rate.
										A value of 0 results in an interrupt when the
										output data is less than the value in the
										THRESH_INACT register.*/

	uint8_t ADXL345_ActInactSetup; /*!<Register 0x27—ACT_INACT_CTL (Read/Write)
										Activity and inactivity setup:
										D7			D6				D5				D4
										ACT ac/dc	ACT_X enable	ACT_Y enable	ACT_Z enable
										D3			D2				D1				D0
										INACT ac/dc	INACT_X enable	INACT_Y enable	INACT_Z enable
										*/

	uint8_t ADXL345_FreeFallThreshold; /*!<Register 0x28—THRESH_FF (Read/Write)
										The THRESH_FF register is eight bits and holds
										the threshold value, in unsigned format, for
										free-fall detection. The acceleration on all axes
										is compared with the value in THRESH_FF to determine
										if a free-fall event occurred. The scale factor
										is 62.5 mg/LSB. Note that a value of 0 mg may result
										in undesirable behavior if the free-fall interrupt
										is enabled. Values between 300 mg and 600 mg
										(0x05 to 0x09) are recommended.*/

	uint8_t ADXL345_FreeFallMinTime;	/*!<Register 0x29—TIME_FF (Read/Write)
										The TIME_FF register is eight bits and stores an
										unsigned time value representing the minimum time
										that the value of all axes must be less than
										THRESH_FF to generate a free-fall interrupt.
										The scale factor is 5 ms/LSB. A value of 0 may
										result in undesirable behavior if the free-fall
										interrupt is enabled. Values between 100 ms and
										350 ms (0x14 to 0x46) are recommended.*/

	uint8_t ADXL345_TapAxesSelect;	/*!<Register 0x2A—TAP_AXES (Read/Write)
									D7			D6				D5				D4
									0			0				0				0
									D3			D2				D1				D0
									Suppress	TAP_X enable	TAP_Y enable	TAP_Z enable
									Suppress Bit
									Setting the suppress bit suppresses double tap
									detection if acceleration greater than the value in
									THRESH_TAP is present between taps. See the Tap
									Detection section for more details.*/

	uint8_t ADXL345_BandwidthRateSelect; /*!<Register 0x2C—BW_RATE (Read/Write)
									D7	D6	D5	D4			| D3	D2	D1	D0
									0	0	0	LOW_POWER	| Rate
									LOW_POWER Bit
									A setting of 0 in the LOW_POWER bit selects normal
									operation, and a setting of 1 selects reduced power
									operation, which has somewhat higher noise (see the
									Power Modes section for details).
									Rate Bits
									These bits select the device bandwidth and output
									data rate (see Table 7 and Table 8 for details). The
									default value is 0x0A, which translates to a 100 Hz
									output data rate. An output data rate should be
									selected that is appropriate for the communication
									protocol and frequency selected. Selecting too high
									of an output data rate with a low communication speed
									results in samples being discarded.*/

	uint8_t ADXL345_PowerControl; /*!<Register 0x2D—POWER_CTL (Read/Write)
									D7	D6	D5		D4			D3		D2		| D1	D0
									0	0	Link	AUTO_SLEEP	Measure	Sleep	| Wakeup*/

	uint8_t ADXL345_IrqEnable; /*!<Register 0x2E—INT_ENABLE (Read/Write)
								D7			D6			D5			D4
								DATA_READY	SINGLE_TAP	DOUBLE_TAP	Activity
								D3			D2			D1			D0
								Inactivity	FREE_FALL	Watermark	Overrun
								Setting bits in this register to a value of 1 enables
								their respective functions to generate interrupts,
								whereas a value of 0 prevents the functions from
								generating interrupts. The DATA_READY, watermark, and
								overrun bits enable only the interrupt output; the
								functions are always enabled. It is recommended that
								interrupts be configured before enabling their outputs.*/

	uint8_t ADXL345_RemapInterruptsToINT2; /*!<Register 0x2F—INT_MAP (R/W)
								Any of the following interrupts should be OR'ed:
								ADXL345_IntMap_DT_RDY
								ADXL345_IntMap_SNGL_TAP
								ADXL345_IntMap_DBL_TAP
								ADXL345_IntMap_Activity
								ADXL345_IntMap_Inactivity
								ADXL345_IntMap_FreeFall
								ADXL345_IntMap_Watermark
								ADXL345_IntMap_Overrun
								the rest of interrupts will automatically
								be mapped to INT1*/

	uint8_t ADXL345_DataFormat; /*!<Register 0x31—DATA_FORMAT (Read/Write)
							D7			D6	D5			D4	D3			D2		| D1	D0
							SELF_TEST	SPI	INT_INVERT	0	FULL_RES	Justify	| Range
							The DATA_FORMAT register controls the presentation of data to
							Register 0x32 through Register 0x37. All data, except that
							for the ±16 g range, must be clipped to avoid rollover.

							Setting
							D1	D0	g Range
							0	0	±2 g
							0	1	±4 g
							1	0	±8 g
							1	1	±16 g*/

	ADXL345_FIFOMode_TypeDef ADXL345_FIFO_Mode; /*!<Register 0x38—FIFO_CTL (Read/Write)
												Select FIFO mode. Must be of
												ADXL345_FIFOMode_TypeDef type*/

	uint8_t ADXL345_TriggerMappingBit; /*!<Trigger Bit
										A value of 0 in the trigger bit links the trigger
										event of trigger mode to INT1, and a value of 1
										links the trigger event to INT2.*/

	uint8_t ADXL345_NumOfSamples; /*!<The function of these bits depends on the FIFO mode selected:

									FIFO Mode	Samples Bits Function
									Bypass		None.
									FIFO		Specifies how many FIFO entries are needed
									 	 	 	 	 to trigger a watermark interrupt.
									Stream		Specifies how many FIFO entries are needed
													to trigger a watermark interrupt.
									Trigger		Specifies how many FIFO samples are
												retained in the FIFO buffer before a
												trigger event.*/





}ADXL345_InitTypeDef;

void ADXL345_Init(ADXL345_InitTypeDef* ADXL345_InitStructure);

/*----------------------------------------------------------------------
The present firmware, which is for guidance only, aims at providing
customers with coding information regarding their products in order
for them to save time. As a result, Analog Devices shall not be
held liable for any direct, indirect, or consequential damages with
respect to any claims arising from the content of such firmware and/or
the use made by customers of the coding information contained herein
in connection with their products.
----------------------------------------------------------------------*/

/* --- I2C addresses --- */
/* The primary slave address is used when the SDO pin is tied or pulled
high. The alternate address is selected when the SDO pin is tied or
pulled low. When building the hardware, if you intend to use I2C,
the state of the SDO pin must be set. The SDO pin is also used for
SPI communication. To save system power, there is no internal pull-up
or pull-down. */
#define XL345_SLAVE_ADDR 0x1d
#define XL345_ALT_ADDR 0x53
/* additional I2C defines for communications functions that need the
address shifted with the read/write bit appended */
#define XL345_SLAVE_READ XL345_SLAVE_ADDR << 1 | 0x01
#define XL345_SLAVE_WRITE XL345_SLAVE_ADDR << 1 | 0x00
#define XL345_ALT_READ XL345_ALT_ADDR << 1 | 0x01
#define XL345_ALT_WRITE XL345_ALT_ADDR << 1 | 0x00
/* ------- Register names ------- */
#define XL345_DEVID 0x00
#define XL345_RESERVED1 0x01
#define XL345_THRESH_TAP 0x1d
#define XL345_OFSX 0x1e
#define XL345_OFSY 0x1f
#define XL345_OFSZ 0x20
#define XL345_DUR 0x21
#define XL345_LATENT 0x22
#define XL345_WINDOW 0x23
#define XL345_THRESH_ACT 0x24
#define XL345_THRESH_INACT 0x25
#define XL345_TIME_INACT 0x26
#define XL345_ACT_INACT_CTL 0x27
#define XL345_THRESH_FF 0x28
#define XL345_TIME_FF 0x29
#define XL345_TAP_AXES 0x2a
#define XL345_ACT_TAP_STATUS 0x2b
#define XL345_BW_RATE 0x2c
#define XL345_POWER_CTL 0x2d
#define XL345_INT_ENABLE 0x2e
#define XL345_INT_MAP 0x2f
#define XL345_INT_SOURCE 0x30
#define XL345_DATA_FORMAT 0x31
#define XL345_DATAX0 0x32
#define XL345_DATAX1 0x33
#define XL345_DATAY0 0x34
#define XL345_DATAY1 0x35
#define XL345_DATAZ0 0x36
#define XL345_DATAZ1 0x37
#define XL345_FIFO_CTL 0x38
#define XL345_FIFO_STATUS 0x39
/*----------------------------------------------------------------------
Bit field definitions and register values
----------------------------------------------------------------------*/
//#define XL345_
/* register values for DEVID */
/* The device ID should always read this value, The customer does not
need to use this value but it can be read to check that the
device can communicate */
#define XL345_ID 0xe5
/* Reserved soft reset value */
#define XL345_SOFT_RESET 0x52
/* Registers THRESH_TAP through TIME_INACT take only 8-bit values
There are no specific bit fields in these registers */
/* Bit values in ACT_INACT_CTL */
#define XL345_INACT_Z_ENABLE 0x01
#define XL345_INACT_Z_DISABLE 0x00
#define XL345_INACT_Y_ENABLE 0x02
#define XL345_INACT_Y_DISABLE 0x00
#define XL345_INACT_X_ENABLE 0x04
#define XL345_INACT_X_DISABLE 0x00
#define XL345_INACT_AC 0x08
#define XL345_INACT_DC 0x00
#define XL345_ACT_Z_ENABLE 0x10
#define XL345_ACT_Z_DISABLE 0x00
#define XL345_ACT_Y_ENABLE 0x20
#define XL345_ACT_Y_DISABLE 0x00
#define XL345_ACT_X_ENABLE 0x40
#define XL345_ACT_X_DISABLE 0x00
#define XL345_ACT_AC 0x80
#define XL345_ACT_DC 0x00
/* Registers THRESH_FF and TIME_FF take only 8-bit values
There are no specific bit fields in these registers */
/* Bit values in TAP_AXES */
#define XL345_TAP_Z_ENABLE 0x01
#define XL345_TAP_Z_DISABLE 0x00
#define XL345_TAP_Y_ENABLE 0x02
#define XL345_TAP_Y_DISABLE 0x00
#define XL345_TAP_X_ENABLE 0x04
#define XL345_TAP_X_DISABLE 0x00
#define XL345_TAP_SUPPRESS 0x08
/* Bit values in ACT_TAP_STATUS */
#define XL345_TAP_Z_SOURCE 0x01
#define XL345_TAP_Y_SOURCE 0x02
#define XL345_TAP_X_SOURCE 0x04
#define XL345_STAT_ASLEEP 0x08
#define XL345_ACT_Z_SOURCE 0x10
#define XL345_ACT_Y_SOURCE 0x20
#define XL345_ACT_X_SOURCE 0x40
/* Bit values in BW_RATE */
/* Expresed as output data rate */
#define XL345_RATE_3200 0x0f
#define XL345_RATE_1600 0x0e
#define XL345_RATE_800 0x0d
#define XL345_RATE_400 0x0c
#define XL345_RATE_200 0x0b
#define XL345_RATE_100 0x0a
#define XL345_RATE_50 0x09
#define XL345_RATE_25 0x08
#define XL345_RATE_12_5 0x07
#define XL345_RATE_6_25 0x06
#define XL345_RATE_3_125 0x05
#define XL345_RATE_1_563 0x04
#define XL345_RATE__782 0x03
#define XL345_RATE__39 0x02
#define XL345_RATE__195 0x01
#define XL345_RATE__098 0x00
/* Expressed as output bandwidth */
/* Use either the bandwidth or rate code,
whichever is more appropriate for your application */
#define XL345_BW_1600 0x0f
#define XL345_BW_800 0x0e
#define XL345_BW_400 0x0d
#define XL345_BW_200 0x0c
#define XL345_BW_100 0x0b
#define XL345_BW_50 0x0a
#define XL345_BW_25 0x09
#define XL345_BW_12_5 0x08
#define XL345_BW_6_25 0x07
#define XL345_BW_3_125 0x06
#define XL345_BW_1_563 0x05
#define XL345_BW__782 0x04
#define XL345_BW__39 0x03
#define XL345_BW__195 0x02
#define XL345_BW__098 0x01
#define XL345_BW__048 0x00
#define XL345_LOW_POWER 0x08
#define XL345_LOW_NOISE 0x00
/* Bit values in POWER_CTL */
#define XL345_WAKEUP_8HZ 0x00
#define XL345_WAKEUP_4HZ 0x01
#define XL345_WAKEUP_2HZ 0x02
#define XL345_WAKEUP_1HZ 0x03
#define XL345_SLEEP 0x04
#define XL345_MEASURE 0x08
#define XL345_STANDBY 0x00
#define XL345_AUTO_SLEEP 0x10
#define XL345_ACT_INACT_SERIAL 0x20
#define XL345_ACT_INACT_CONCURRENT 0x00
/* Bit values in INT_ENABLE, INT_MAP, and INT_SOURCE are identical.
Use these bit values to read or write any of these registers. */
#define XL345_OVERRUN 0x01
#define XL345_WATERMARK 0x02
#define XL345_FREEFALL 0x04
#define XL345_INACTIVITY 0x08
#define XL345_ACTIVITY 0x10
#define XL345_DOUBLETAP 0x20
#define XL345_SINGLETAP 0x40
#define XL345_DATAREADY 0x80
/* Bit values in DATA_FORMAT */
/* Register values read in DATAX0 through DATAZ1 are dependent on the
value specified in data format. Customer code will need to interpret
the data as desired. */
#define XL345_RANGE_2G 0x00
#define XL345_RANGE_4G 0x01
#define XL345_RANGE_8G 0x02
#define XL345_RANGE_16G 0x03
#define XL345_DATA_JUST_RIGHT 0x00
#define XL345_DATA_JUST_LEFT 0x04
#define XL345_10BIT 0x00
#define XL345_FULL_RESOLUTION 0x08
#define XL345_INT_LOW 0x20
#define XL345_INT_HIGH 0x00
#define XL345_SPI3WIRE 0x40
#define XL345_SPI4WIRE 0x00
#define XL345_SELFTEST 0x80
/* Bit values in FIFO_CTL */
/* The low bits are a value 0 to 31 used for the watermark or the number of pre-trigger samples when in triggered mode */
#define XL345_TRIGGER_INT1 0x00
#define XL345_TRIGGER_INT2 0x20
#define XL345_FIFO_MODE_BYPASS 0x00
#define XL345_FIFO_RESET 0x00
#define XL345_FIFO_MODE_FIFO 0x40
#define XL345_FIFO_MODE_STREAM 0x80
#define XL345_FIFO_MODE_TRIGGER 0xc0
/* Bit values in FIFO_STATUS */
/* The low bits are a value 0 to 32 showing the number of entries
currently available in the FIFO buffer */
#define XL345_FIFO_TRIGGERED 0x80


#endif