; Atmel AVR Disassembler v1.30 ; .include "tn26def.inc" ;.device tiny26 ;.eseg .DEF rd1l = R0 ; LSB 16-bit-number to be divided .DEF rd1h = R1 ; MSB 16-bit-number to be divided .DEF rd1u = R2 ; interim register .DEF rd2 = R3 ; 8-bit-number to divide with .DEF rel = R4 ; LSB result .DEF reh = R5 ; MSB result .DEF rmp = R17; multipurpose register for loading .equ del = 0x8 ; .equ del1 = 0x02 ; .cseg .org 0 SS: .db 0xF9,0xff,0x00,0x00,0xf1,0xff,0x00,0x00 A0000000: rjmp A000001A A0000002: reti A0000004: reti A0000006: reti A0000008: reti A000000A: reti A000000C: reti A000000E: reti A0000010: reti A0000012: reti A0000014: reti A0000016: reti A0000018: reti A000001A: cli A000001C: clr r16 A000001E: out DDRB,r16 A0000020: out DDRA,r16 A0000022: ldi r16,0xDF;#223 A0000024: out SP,r16;spl A0000026: wdr A0000028: ldi r16,0x08;#8 A000002A: out WDTCR,r16 A000002C: ldi r16,0x20;#32 A000002E: out MCUCR,r16 A0000030: ldi r16,0x80;#128 A0000032: out ACSR,r16 A0000034: ldi r16,0xC0;#192 A0000036: out OSCCAL,r16;OCR0 A0000038: sei A000003A: wdr A000003C: clr r15 A000003E: ldi r23,0x8C;#140 A0000040: out ADCSR,r15 A0000042: ldi r17,0x8B;#139 A0000044: out ADMUX,r17 A0000046: out ADCSR,r23 A0000048: sbi ADCSR,6 A000004A: sleep A000004C: in r16,ADCL A000004E: in r18,ADCH A0000050: out ADCSR,r15 A0000052: ldi r17,0x99;#153 A0000054: out ADMUX,r17 A0000056: out ADCSR,r23 A0000058: sbi ADCSR,6 A000005A: sleep A000005C: in r17,ADCL A000005E: in r19,ADCH A0000060: ldi r31, high(SS) ;0x03;#3 A0000062: ldi r30,low(SS+6); 0xC0;#192 A0000064: lpm A0000066: inc r30 A0000068: mov r1,r0 A000006A: lpm A000006C: sub r16,r17 A000006E: sbc r18,r19 A0000070: add r16,r1 A0000072: adc r18,r0 A0000074: sbrs r18,7 A0000076: rjmp A0000088 A0000078: ldi r22,0x03;#3 A000007A: ror r18 A000007C: ror r16 A000007E: ror r18 A0000080: ror r16 A0000082: neg r16 A0000084: mov r18,r16 A0000086: rjmp A0000094 A0000088: ldi r22,0x01;#1 01 A000008A: ror r18 A000008C: ror r16 A000008E: ror r18 A0000090: ror r16 A0000092: mov r18,r16 A0000094: out ADCSR,r15 A0000096: ldi r17,0x97;#151 A0000098: out ADMUX,r17 A000009A: out ADCSR,r23 A000009C: sbi ADCSR,6 A000009E: sleep A00000A0: in r16,ADCL A00000A2: in r20,ADCH A00000A4: out ADCSR,r15 A00000A6: ldi r17,0x92;#146 A00000A8: out ADMUX,r17 A00000AA: out ADCSR,r23 A00000AC: sbi ADCSR,6 A00000AE: sleep A00000B0: in r17,ADCL A00000B2: in r21,ADCH A00000B4: ldi r31,high(SS);0x03;#3 A00000B6: ldi r30,low(SS+4);0xE0;#224 A00000B8: lpm A00000BA: inc r30 A00000BC: mov r1,r0 A00000BE: lpm A00000C0: sub r16,r17 A00000C2: sbc r20,r21 A00000C4: add r16,r1 A00000C6: adc r20,r0 A00000C8: sbrs r20,7 A00000CA: rjmp A00000E0 A00000CC: cpi r22,0x01;#1 A00000CE: breq A00000D2 A00000D0: ldi r22,0x04;#4 A00000D2: ror r20 A00000D4: ror r16 A00000D6: ror r20 A00000D8: ror r16 A00000DA: neg r16 A00000DC: mov r20,r16 A00000DE: rjmp A00000F0 A00000E0: cpi r22,0x03;#3 A00000E2: breq A00000E6 A00000E4: ldi r22,0x02;#2 A00000E6: ror r20 A00000E8: ror r16 A00000EA: ror r20 A00000EC: ror r16 A00000EE: mov r20,r16 A00000F0: mov r1,r18 A00000F2: mov r2,r20 A00000F4: clr r0 A00000F6: add r2,r1 A00000F8: rol r0 A00000FA: mov r6,r0 A00000FC: mov r7,r2 A00000FE: ser r16 A0000100: mov r4,r16 A0000102: mov r5,r16 A0000104: rcall A000020A A0000106: clr r6 A0000108: mov r7,r18 A000010A: rcall A000024C A000010C: mov r24,r4 A000010E: mov r1,r18 A0000110: mov r2,r20 A0000112: clr r0 A0000114: add r2,r1 A0000116: rol r0 A0000118: mov r6,r0 A000011A: mov r7,r2 A000011C: ser r16 A000011E: mov r4,r16 A0000120: mov r5,r16 A0000122: rcall A000020A A0000124: clr r6 A0000126: mov r7,r20 A0000128: rcall A000024C A000012A: ser r16 A000012C: sub r16,r4 A000012E: add r16,r24 A0000130: ror r16 A0000132: mov r4,r16 A0000134: cpi r22,0x01;#1 A0000136: breq A0000184 A0000138: cpi r22,0x02;#2 A000013A: breq A0000188 A000013C: cpi r22,0x03;#3 A000013E: breq A0000192 A0000140: rjmp A0000196 A0000142: mov r16,r4 A0000144: cpi r16,0x64;#64 40 A0000146: brlo A000015E A0000148: cpi r16,0x80;#128 80 A000014A: brlo A0000168 A000014C: cpi r16,0xc0;#192 c0 A000014E: brlo A0000176 A0000150: ser r17 A0000152: sub r17,r16 A0000154: lsr r17 A0000156: lsr r17 A0000158: lsr r17 A000015A: add r4,r17 A000015C: ret A000015E: lsr r16 A0000160: lsr r16 A0000162: lsr r16 A0000164: sub r4,r16 A0000166: ret A0000168: ldi r17,0x7f;#127; 7f A000016A: sub r17,r16 A000016C: lsr r17 A000016E: lsr r17 A0000170: lsr r17 A0000172: sub r4,r17 A0000174: ret A0000176: ldi r17,0x80;#128;80 A0000178: sub r16,r17 A000017A: lsr r16 A000017C: lsr r16 A000017E: lsr r16 A0000180: add r4,r16 A0000182: ret A0000184: rcall A0000142 A0000186: rjmp A000019E A0000188: ser r16 A000018A: sub r16,r4 A000018C: mov r4,r16 A000018E: rcall A0000142 A0000190: rjmp A000019E A0000192: rcall A0000142 A0000194: rjmp A000019E A0000196: ser r16 A0000198: sub r16,r4 A000019A: mov r4,r16 A000019C: rcall A0000142 A000019E: ldi r31,high(SS);0x03;#3 A00001A0: ldi r30,low(SS+2);0xA0;#160 A00001A2: lpm A00001A4: inc r30 A00001A6: mov r1,r0 A00001A8: lpm A00001AA: dec r22 A00001AC: add r4,r1 A00001AE: adc r22,r0 A00001B0: andi r22,0x03; #$3 A00001B2: inc r22 A00001B4: cpi r22,0x01;#1 A00001B6: breq A00001C2 A00001B8: cpi r22,0x02;#2 A00001BA: breq A00001CE A00001BC: cpi r22,0x03;#3 A00001BE: breq A00001DA A00001C0: rjmp A00001F0 A00001C2: ldi r16,0x00; #0 A00001C4: mov r6,r16 A00001C6: mov r7,r4 A00001C8: rcall A000026A A00001CA: mov r0,r4 A00001CC: rjmp A00001F2 A00001CE: ldi r16,0x01;#1 A00001D0: mov r6,r16 A00001D2: mov r7,r4 A00001D4: rcall A000026A A00001D6: mov r0,r4 A00001D8: rjmp A00001F2 A00001DA: ldi r16,0x02;#2 A00001DC: mov r6,r16 A00001DE: mov r7,r4 A00001E0: rcall A000026A A00001E2: ldi r16,0xE1;#225;e1 A00001E4: cp r4,r16 A00001E6: brsh A00001EC A00001E8: mov r0,r4 A00001EA: rjmp A00001F2 A00001EC: mov r0,r16 A00001EE: rjmp A00001F2 A00001F0: clr r0 A00001F2: ldi r16,0x0d;#13; 0d A00001F4: add r0,r16 A00001F6: mov r26,r0 A00001F8: ser r16 push r26 push r16 ; // второй канал, начало ; mov rmp,r26 ; ; rcall devide ; деление текущего значения ; push r18 ; ; add r26,r1 ; добавляется смещение (угол) ldi r17,0x00 ; ldi r18,0xf1 sub r18,r26 brcs ff sub r26,r18 brcs ff sub r26,r18 brcs ff sub r26,r18 brcs ff sub r26,r18 brcs ff sub r26,r18 ;sub r26,r18 brcs ff ldi r18,0x09 sub r26,r18 brcs ff ; rjmp A0000201 cp r26,r17 brcc rrr ff: mov r26,r17 sbis PINA,2 ldi r26,0xf1 ldi r26,0xff ; ограничение rrr: pop r16 A00001FA: out OCR1C,r16;ocr1ah ; канал 1 A00001FC: ldi r16,0xA3;#130 82 A00001FE: out TCCR1A,r16;ASSR A0000200: ldi r16,0x01;#1 A0000206: out OCR1A,r26 ;tcnt1h pop r26 ldi r17,0xff sub r17,r26 mov rmp,r17 ; загрузка rcall devide ; деление текущего значения sub r26,r5 ; добавляется смещение (угол) A0000201: out OCR1B,r26 ; канал газа A0000202: out TCCR1B,r16 A0000204: ; sbi DDRB,1 ldi r16, 0x0f out DDRB,r16 ; // второй канал, конец A0000208: rjmp A000003A A000020A: clr r8 A000020C: clr r9 A000020E: clr r16 A0000210: cp r6,r16 A0000212: brne A000021A A0000214: cp r7,r16 A0000216: brne A000021A A0000218: inc r7 A000021A: rcall A000023E A000021C: inc r9 A000021E: sub r5,r7 A0000220: sbc r4,r6 A0000222: brsh A000022A A0000224: add r5,r7 A0000226: adc r4,r6 A0000228: dec r9 A000022A: dec r16 A000022C: breq A000023C A000022E: clc A0000230: rol r9 A0000232: rol r8 A0000234: clc A0000236: ror r6 A0000238: ror r7 A000023A: rjmp A000021C A000023C: ret A000023E: inc r16 A0000240: sbrc r6,7 A0000242: ret A0000244: clc A0000246: rol r7 A0000248: rol r6 A000024A: rjmp A000023E A000024C: clr r4 A000024E: clr r5 A0000250: ldi r16,0x12;#12;0c A0000252: ror r8 A0000254: ror r9 A0000256: brsh A000025C A0000258: add r5,r7 A000025A: adc r4,r6 A000025C: dec r16 A000025E: breq A0000268 A0000260: clc A0000262: rol r7 A0000264: rol r6 A0000266: rjmp A0000252 A0000268: ret A000026A: ldi r31,high(SS);0x03;#3 A000026C: ldi r30,low(SS);0x80;#128 A000026E: lpm A0000270: inc r30 A0000272: mov r9,r0 A0000274: lpm A0000276: ser r16 A0000278: cp r0,r16 A000027A: breq A0000280 A000027C: mov r8,r0 A000027E: rjmp A0000288 A0000280: ldi r16,0x05;#5 A0000282: mov r8,r16 A0000284: ldi r16,0x00;#0 A0000286: mov r9,r16 A0000288: clr r10 A000028A: clr r3 A000028C: clr r4 A000028E: clr r5 A0000290: ldi r16,0x0B;#11 A0000292: ror r8 A0000294: ror r9 A0000296: brsh A000029E A0000298: add r5,r7 A000029A: adc r4,r6 A000029C: adc r3,r10 A000029E: dec r16 A00002A0: breq A00002AC A00002A2: clc A00002A4: rol r7 A00002A6: rol r6 A00002A8: rol r10 A00002AA: rjmp A0000292 A00002AC: ror r3 A00002AE: ror r4 A00002B0: ror r3 A00002B2: ror r4 A00002B4: ror r3 A00002B6: ror r4 A00002B8: ror r3 A00002BA: ror r4 A00002BC: ret ; devide: ; ; Load the test numbers to the appropriate registers ; push r0 push r1 push r2 push r3 push r4 push r17 ; ldi rmp,del; 0xAAAA to be divided mov rd1h,rmp mov rd1l,rmp ldi rmp,del1; 0x55 to be divided with mov rd2,rmp ; ; Divide rd1h:rd1l by rd2 ; div8: clr rd1u ; clear interim register clr reh ; clear result (the result registers clr rel ; are also used to count to 16 for the inc rel ; division steps, is set to 1 at start) ; ; Here the division loop starts ; div8a: clc ; clear carry-bit rol rd1l ; rotate the next-upper bit of the number rol rd1h ; to the interim register (multiply by 2) rol rd1u brcs div8b ; a one has rolled left, so subtract cp rd1u,rd2 ; Division result 1 or 0? brcs div8c ; jump over subtraction, if smaller div8b: sub rd1u,rd2; subtract number to divide with sec ; set carry-bit, result is a 1 rjmp div8d ; jump to shift of the result bit div8c: clc ; clear carry-bit, resulting bit is a 0 div8d: rol rel ; rotate carry-bit into result registers rol reh brcc div8a ; as long as zero rotate out of the result ; registers: go on with the division loop ; End of the division reached ; stop: ; rjmp stop ; endless loop pop r17 pop r4 pop r3 pop r2 pop r1 pop r0 ret