bldc.h

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00013 
00014 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
00015  *
00016  * Redistribution and use in source and binary forms, with or without
00017  * modification, are permitted provided that the following conditions are met:
00018  *
00019  * 1. Redistributions of source code must retain the above copyright notice,
00020  * this list of conditions and the following disclaimer.
00021  *
00022  * 2. Redistributions in binary form must reproduce the above copyright notice,
00023  * this list of conditions and the following disclaimer in the documentation
00024  * and/or other materials provided with the distribution.
00025  *
00026  * 3. The name of ATMEL may not be used to endorse or promote products derived
00027  * from this software without specific prior written permission.
00028  *
00029  * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
00030  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00031  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
00032  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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00040  
00041 #ifndef _BLDC_H_
00042 #define _BLDC_H_
00043 
00044 //_____  I N C L U D E S ___________________________________________________
00045 #include "config.h"
00046 
00047 //_____ M A C R O S ________________________________________________________
00048 
00049 //_____ D E F I N I T I O N S ______________________________________________
00050 
00052 #define EDGE_FALLING                  1
00053 
00055 #define EDGE_RISING                   0
00056 
00058 #define CW                            0
00059 
00061 #define CCW                           1
00062 
00064 #define DRIVE_PATTERN_STEP1_CCW      ((1 << UL) | (1 << VH))
00065 
00067 #define DRIVE_PATTERN_STEP2_CCW      ((1 << UL) | (1 << WH))
00068 
00070 #define DRIVE_PATTERN_STEP3_CCW      ((1 << VL) | (1 << WH))
00071 
00073 #define DRIVE_PATTERN_STEP4_CCW      ((1 << VL) | (1 << UH))
00074 
00076 #define DRIVE_PATTERN_STEP5_CCW      ((1 << WL) | (1 << UH))
00077 
00079 #define DRIVE_PATTERN_STEP6_CCW      ((1 << WL) | (1 << VH))
00080 
00081 
00083 #define DRIVE_PATTERN_STEP1_CW      ((1 << VH) | (1 << WL))
00084 
00086 #define DRIVE_PATTERN_STEP2_CW      ((1 << UH) | (1 << WL))
00087 
00089 #define DRIVE_PATTERN_STEP3_CW      ((1 << UH) | (1 << VL))
00090 
00092 #define DRIVE_PATTERN_STEP4_CW      ((1 << WH) | (1 << VL))
00093 
00095 #define DRIVE_PATTERN_STEP5_CW      ((1 << WH) | (1 << UL))
00096 
00098 #define DRIVE_PATTERN_STEP6_CW      ((1 << VH) | (1 << UL))
00099 
00101 #define PWM_TOP_VALUE               255
00102 
00104 #define MIN_PWM_COMPARE_VALUE       160
00105 
00107 #define MAX_PWM_COMPARE_VALUE       PWM_TOP_VALUE
00108 
00110 #define STARTUP_PWM_COMPARE_VALUE   140
00111 
00112 
00113 //ADC MUX setting to select PA7.
00114 #define ADMUX_PA7   ((1 << MUX2) | (1 << MUX1) | (1 << MUX0))
00115 #define ADMUX_PA1   ((0 << MUX2) | (0 << MUX1) | (1 << MUX0))
00116 #define ADMUX_PA2   ((0 << MUX2) | (1 << MUX1) | (0 << MUX0))
00117 #define ADMUX_PA4   ((0 << MUX2) | (1 << MUX1) | (1 << MUX0))
00118 #define ADMUX_PA5   ((1 << MUX2) | (0 << MUX1) | (0 << MUX0))
00119 
00121 #define ADC_RES_ALIGNMENT_BEMF          (0 << ADLAR)
00122 
00124 #define ADC_RES_ALIGNMENT_SPEED_REF     (0 << ADLAR)
00125 
00127 #define ADC_RES_ALIGNMENT_CURRENT       (0 << ADLAR)
00128 
00130 #define ADC_RES_ALIGNMENT_REF_VOLTAGE   (0 << ADLAR)
00131 
00133 #define ADMUX_U             (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_BEMF | ADC_MUX_U)
00134 
00136 #define ADMUX_V             (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_BEMF | ADC_MUX_V)
00137 
00139 #define ADMUX_W             (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_BEMF | ADC_MUX_W)
00140 
00142 #define ADMUX_REF_VOLTAGE   (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_REF_VOLTAGE | ADC_MUX_SPEED_REF)
00143 
00145 #define ADMUX_SPEED_REF     (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_SPEED_REF | ADC_MUX_SPEED_REF)
00146 
00148 #define ADC_PRESCALER       ADC_PRESCALER_8
00149 
00151 #define ADC_TRIGGER_SOURCE  ((1 << ADTS2) | (1 << ADTS1) | (0 << ADTS0))
00152 
00154 #define ADC_ZC_THRESHOLD    371
00155 
00157 #define SET_TIMER0_INT_COMMUTATION    SET_TIMER0_COMPA_INT
00158 
00159 #endif //_BLDC_H_

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