00001
00024
00025 void USI_TWI_Slave_Initialise( unsigned char );
00026 void USI_TWI_Transmit_Byte( unsigned char byte_data);
00027 unsigned char USI_TWI_Receive_Byte( void );
00028 unsigned char USI_TWI_Data_In_Receive_Buffer( void );
00029 void Timer_Init(void);
00030
00031
00032
00033
00034 typedef unsigned char uint8_t;
00035
00039
00040
00041 #define TWI_RX_BUFFER_SIZE (16)
00042 #define TWI_RX_BUFFER_MASK ( TWI_RX_BUFFER_SIZE - 1 )
00043
00044 #if ( TWI_RX_BUFFER_SIZE & TWI_RX_BUFFER_MASK )
00045 #error TWI RX buffer size is not a power of 2
00046 #endif
00047
00048
00049
00050 #define TWI_TX_BUFFER_SIZE (16)
00051 #define TWI_TX_BUFFER_MASK ( TWI_TX_BUFFER_SIZE - 1 )
00052
00053 #if ( TWI_TX_BUFFER_SIZE & TWI_TX_BUFFER_MASK )
00054 #error TWI TX buffer size is not a power of 2
00055 #endif
00056
00057
00058
00059 #define USI_SLAVE_CHECK_ADDRESS (0x00)
00060 #define USI_SLAVE_SEND_DATA (0x01)
00061 #define USI_SLAVE_REQUEST_REPLY_FROM_SEND_DATA (0x02)
00062 #define USI_SLAVE_CHECK_REPLY_FROM_SEND_DATA (0x03)
00063 #define USI_SLAVE_REQUEST_DATA (0x04)
00064 #define USI_SLAVE_GET_DATA_AND_SEND_ACK (0x05)
00065
00066
00068 #if defined(__AT90tiny26__) | defined(__ATtiny26__)
00069 #define DDR_USI DDRB
00070 #define PORT_USI PORTB
00071 #define PIN_USI PINB
00072 #define PORT_USI_SDA PORTB0
00073 #define PORT_USI_SCL PORTB2
00074 #define PIN_USI_SDA PINB0
00075 #define PIN_USI_SCL PINB2
00076 #define USI_START_COND_INT USISIF
00077 #define USI_START_VECTOR USI_STRT_vect
00078 #define USI_OVERFLOW_VECTOR USI_OVF_vect
00079 #endif
00080
00082 #if defined(__AT90tiny861__) | defined(__ATtiny861__) | defined (__AVR_ATtiny861__)
00083 #define DDR_USI DDRA
00084 #define PORT_USI PORTA
00085 #define PIN_USI PINA
00086 #define PORT_USI_SDA PORTA0
00087 #define PORT_USI_SCL PORTA2
00088 #define PIN_USI_SDA PINA0
00089 #define PIN_USI_SCL PINA2
00090 #define USI_START_COND_INT USISIF
00091 #define USI_START_VECTOR USI_START_vect
00092 #define USI_OVERFLOW_VECTOR USI_OVF_vect
00093 #endif
00094
00095 #if defined(__AT90Tiny2313__) | defined(__ATtiny2313__)
00096 #define DDR_USI DDRB
00097 #define PORT_USI PORTB
00098 #define PIN_USI PINB
00099 #define PORT_USI_SDA PORTB5
00100 #define PORT_USI_SCL PORTB7
00101 #define PIN_USI_SDA PINB5
00102 #define PIN_USI_SCL PINB7
00103 #define USI_START_COND_INT USISIF
00104 #define USI_START_VECTOR USI_STRT_vect
00105 #define USI_OVERFLOW_VECTOR USI_OVF_vect
00106 #endif
00107
00108 #if defined(__ATtiny25__) | defined(__ATtiny45__) | defined(__ATtiny85__)
00109 #define DDR_USI DDRB
00110 #define PORT_USI PORTB
00111 #define PIN_USI PINB
00112 #define PORT_USI_SDA PORTB0
00113 #define PORT_USI_SCL PORTB2
00114 #define PIN_USI_SDA PINB0
00115 #define PIN_USI_SCL PINB2
00116 #define USI_START_COND_INT USICIF
00117 #define USI_START_VECTOR USI_START_vect
00118 #define USI_OVERFLOW_VECTOR USI_OVF_vect
00119 #endif
00120
00121 #if defined(__AT90Mega165__) | defined(__ATmega165__) | \
00122 defined(__ATmega325__) | defined(__ATmega3250__) | \
00123 defined(__ATmega645__) | defined(__ATmega6450__) | \
00124 defined(__ATmega329__) | defined(__ATmega3290__) | \
00125 defined(__ATmega649__) | defined(__ATmega6490__)
00126 #define DDR_USI DDRE
00127 #define PORT_USI PORTE
00128 #define PIN_USI PINE
00129 #define PORT_USI_SDA PORTE5
00130 #define PORT_USI_SCL PORTE4
00131 #define PIN_USI_SDA PINE5
00132 #define PIN_USI_SCL PINE4
00133 #define USI_START_COND_INT USISIF
00134 #define USI_START_VECTOR USI_START_vect
00135 #define USI_OVERFLOW_VECTOR USI_OVERFLOW_vect
00136 #endif
00137
00138 #if defined(__AT90Mega169__) | defined(__ATmega169__)
00139 #define DDR_USI DDRE
00140 #define PORT_USI PORTE
00141 #define PIN_USI PINE
00142 #define PORT_USI_SDA PORTE5
00143 #define PORT_USI_SCL PORTE4
00144 #define PIN_USI_SDA PINE5
00145 #define PIN_USI_SCL PINE4
00146 #define USI_START_COND_INT USISIF
00147 #define USI_START_VECTOR USI_STRT_vect
00148 #define USI_OVERFLOW_VECTOR USI_OVF_vect
00149 #endif
00150
00152 #define SET_USI_TO_SEND_ACK() \
00153 { \
00154 USIDR = 0; \
00155 DDR_USI |= (1<<PORT_USI_SDA); \
00156 USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| \
00157 (0x0E<<USICNT0); \
00158 }
00159
00160 #define SET_USI_TO_READ_ACK() \
00161 { \
00162 DDR_USI &= ~(1<<PORT_USI_SDA); \
00163 USIDR = 0; \
00164 USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| \
00165 (0x0E<<USICNT0); \
00166 }
00167
00168 #define SET_USI_TO_TWI_START_CONDITION_MODE() \
00169 { \
00170 USICR = (1<<USISIE)|(0<<USIOIE)| \
00171 (1<<USIWM1)|(0<<USIWM0)| \
00172 (1<<USICS1)|(0<<USICS0)|(0<<USICLK)| \
00173 (0<<USITC); \
00174 USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| \
00175 (0x0<<USICNT0); \
00176 }
00177
00178 #define SET_USI_TO_SEND_DATA() \
00179 { \
00180 DDR_USI |= (1<<PORT_USI_SDA); \
00181 USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| \
00182 (0x0<<USICNT0); \
00183 }
00184
00185 #define SET_USI_TO_READ_DATA() \
00186 { \
00187 DDR_USI &= ~(1<<PORT_USI_SDA); \
00188 USISR = (0<<USI_START_COND_INT)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| \
00189 (0x0<<USICNT0); \
00190 }